1. Field of the Invention
The present invention relates to a semiconductor device which is designed for use in a a hybrid LSI (Large-Scale Integrated) circuit, and which comprises bipolar transistors and a MOSFET, and more particularly a semiconductor device which comprises bipolar transistors and a MOSFET whose characteristic remains unchanged, and which is therefore greatly resistant to soft errors.
2. Description of the Related Art
Semiconductor devices have been used, each of which can be used for constituting a hybrid LSI (Large-Scale Integrated) circuit and comprises bipolar transistors and MOSFETs.
FIG. 1 is a sectional view illustrating a conventional semiconductor device for use in a hybrid LSI circuit. This device which comprises a bipolar transistor and two MOSFETs. As this figure shows, a N.sup.+ -type buried layer 12 and a P.sup.+ -type buried diffusion layer 14, both having a high impurity concentration, are formed in a P-type silicon substrate 10. A P-type epitaxial layer 16 is also formed on the P-type silicon substrate 10. N-type well-regions 18a and 18b are formed in those portions of the P-type epitaxial layer 16 which are located on the N.sup.+ -type buried layer 12. The first P-channel MOSFET and the bipolar transistor are formed in the N-type well-regions 18a and 18b, respectively. A P-type well-region 20 is formed in that portion of the P-type epitaxial layer 16 which is located on the P.sup.+ -type buried layer 14 and in which a field oxide film 22 is formed. The field oxide film 22 functions as a element-isolating region.
P-type source/drain regions 24 are formed in the N-type well-region 18a in which the P-channel MOSFET is formed. That portion of the N-type well-region 18a, which is located between the P-type source/drain regions 24, is a channel region. A gate-oxide film 26 is formed on this channel region, and a gate electrode 28 is formed on the gate-oxide film 26. An insulating film 30 is formed on the sides of the gate-oxide film 26 and the gate electrode 28, and is used as a side-wall spacer.
N-type source/drain regions 32 are formed in the P-type well-region 20 in which the second N-channel MOSFET is formed. The second N-channel MOSFET is of the so-called LDD structure, and its source an drain have a high breakdown voltage. Thus, as is evident from FIG. 1, N.sup.- -type source/drain regions 34 having a low impurity concentration are formed in contact with the N-type source/drain regions 32, respectively. That portion of the P-type well-region 20 which is located between the N.sup.- -type source/drain regions 34 is a channel region. A gate-oxide film 26 is formed on this channel region, and a gate electrode 28 is formed on the gate-oxide film 26. An insulating film 30 is formed on the sides of the gate-oxide film 26 and the gate electrode 28, and is used as a side-wall spacer. Also, a P.sup.- -type inversion-preventing layer 36 having a low impurity concentration is formed below the field oxide film 22 formed in the surface of the P-type well-region 20.
The N-type well-region 18b, in which the bipolar transistor is formed, functions as the collector of this bipolar transistor. A P.sup.+ -type external base region 38, which has a high impurity concentration, is formed in the N-type well-region 18b. A P-type internal base region 40 is formed also in the N-type well-region 18b. The region 40 contacts with the P.sup.+ -type external base region 38. An N-type emitter region 42 is formed in a part of the P-type internal base region 40. An emitter electrode 44 made of polysilicon is formed on the N-type emitter region 42. As is shown in FIG. 1, an insulating film 46 electrically isolates the emitter electrode 44 from the P-type internal base region 40. Also, an N.sup.+ -type external collector region 48 is formed on one portion of the N.sup.+ -type buried layer 12, in contact therewith.
An inter-layer insulating film 50 is formed on the entire surface of the P-type epitaxial layer 16, including the element-forming regions in which the bipolar transistor, the P-channel MOSFET and the N-type MOSFET. Source/drain electrodes 52, both made of aluminum, are formed on those portions of the film 50 which are located on the P-type source/drain region 24 of the P-channel MOSFET and the N-type source/drain region 32 of the N-channel MOSFET. These electrodes 52 extend through contact holes made in the inter-layer insulating film 50 and are electrically connected to the source/drain regions 24 and 32, respectively. An emitter electrode 54, also made of aluminum, is formed on that portion of the film 50 which is located on the emitter 44 of the bipolar transistor. This electrode 54 extends through a contact hole made in the film 50 and is electrically connected to the emitter 44. A collector electrode 56, also made of aluminum, is formed on that portion of the film 50 which is located on the N.sup.30 -type external collector region 48. The collector electrode 56 extends through a contact hole cut in the film 50 and is electrically connected to the external collector region 48.
The conventional semiconductor device described above has an N-type well-regions 18a and 18b in the P-type epitaxial layer 16, so that a P-channel MOSFET and a bipolar transistor are formed in these N-type well-regions 18a and 18b, respectively. To simplify the process of manufacturing the semiconductor device, those portions of the layer 16 which correspond to the well-regions 18a and 18b simultaneously undergo impurity-ion injection, and also simultaneously undergo impurity diffusion.
FIG. 2 is graph which represents the impurity-concentration profile of the N-type well-regions 18a and 18b of the prior-art semiconductor device, in which the P-channel MOSFET and the bipolar transistor are formed, respectively. As can be clearly understood from the graph of FIG. 2, the N-type regions 18a and 18b have an identical impurity-concentration profile. The well-region 18a, which the P-channel MOSFET is formed, has a impurity concentration high enough to suppress the so-called "short-channel effect" resulting from the micro-processing of the P-channel MOSFET. Since the well-region 18b is formed along with the well-region 18a, in the same step, it also has a high impurity concentration. Hence, the collector of the bipolar transistor, which is formed in the well-region 18b, also has a high impurity concentration.
The higher the impurity concentration of the collector of the bipolar transistor, the higher the cutoff frequency f.sub.T of the bipolar transistor, which is a fundamental property of a bipolar transistor. Thus, the high-frequency characteristic of the bipolar transistor is improved in proportion to the cutoff frequency f.sub.T. However, the higher the impurity concentration of the collector, the lower the base-collector breakdown voltage BV.sub.CBO and the early voltage V.sub.AF of the bipolar transistor. In other words, the breakdown voltage of the bipolar transistor decreases in inverse proportion to the cutoff frequency f.sub.T. So do the amplification factor and linear characteristic of the bipolar transistor.
As has been described, the N-type well-regions 18a and 18b are formed by diffusing an N-type impurity into the P-type epitaxial layer 16. When the P-type epitaxial layer 16 is heated at high temperature for a long time to impart a sufficiently high impurity concentration to, particularly, the well-region 18a, the impurity concentration of the P.sup.+ -type buried diffusion layer 14 inevitably decreases. Consequently, the buried diffusion layer 14 cannot completely prevent a punch-through between the N-type well-regions 18a and 18b.
FIG. 3 is a graph representing the impurity-concentration profile of the P-type well-region 20 in which the N-channel MOSFET is formed. As is evident from this figure, the concentration of the P-type impurity in the P.sup.+ -type buried diffusion layer 14 decreases toward the substrate 10. This is because the P-type impurity diffuses from the layer 14 into the P-type well-region 20 which is located on the layer 14 and has a impurity concentration lower than that of the buried layer 14. As a result, the impurity concentration of the P-type well-region 20 increases in excess, inevitably altering the characteristic of the N-channel MOSFET formed in the P-type well-region 20.
When a number of semiconductor devices identical to the device described above are used, together with other components, thus constituting a memory LSI, the impurity concentration of each P.sup.+ -type buried layer 14 will becomes almost the same as that of the P-type silicon substrate 10. This implies that the memory LSI is likely to have soft errors due to the .alpha.-rays generated by the fission of uranium contained, in a very small amount, in the package material of the memory LSI.